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Semiconductor Design & Verification Services

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VESA Display Stream Compression (DSC) Decoder
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Implemented and verified DSC Decoder with golden-model checks over all standard modes.
Coded RTL for decoder blocks (ICH, RGB↔YCoCg, P-Mode, MMAP/MPP, InvQuant, DSU VLD units, PPS regs). Verified against a C++ reference model with coverage-driven UVM tests across RGB/YUV444/422/420 and 8–bit to 16-bit depths.
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