Insights

Implemented Verilog RTL for core encoder blocks (ICH, RGB↔YCoCg, P-Mode/MMAP/MPP, Quant/InvQuant, DSU VLC, PPS register file). Built a UVM environment with reference model, assertions, and coverage to validate multiple formats (RGB, YUV444, Simple422, Native422/420) and BPC/BPP combinations.