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Semiconductor Design & Verification Services
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USB 2.0 UTMI PHY & SIE
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Built a USB2.0 soft-PHY and verified UTMI PHY + SIE behavior on FPGA.
Wrote Verilog RTL for a USB2.0 soft PHY (Gowin). Verified protocol transactions, error handling and link states with functional testbenches and simulation debugging.
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