Formal Verification

Background

Assertion-based property checking for design reliability.

Using SystemVerilog Assertions (SVA) and formal tools, we mathematically verify that the design meets all functional requirements, eliminating hidden corner-case bugs.

Case Study

The Problem

Simulation cannot cover all corner cases in complex designs.

Our Solutions

Formal verification guarantees exhaustive property checking, reducing risk of silicon re-spins.

Related Insights

USB 2.0 UTMI PHY & SIE

Built a USB2.0 soft-PHY and verified UTMI PHY + SIE behavior on FPGA.

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